The present invention relates to a frequency synthesizer having a fractional divider and a corresponding frequency synthesizing method.
The invention more particularly relates to a frequency synthesizer permitting a precise adjustment of the frequency and capable of rapidly switching between various selected frequencies one after the other.
Such a frequency synthesizer may be used in various types of radio circuits and, more particularly, in receiving and/or transmitting stages of these circuits. By way of example the frequency synthesizer according to the invention may be used in cordless telephony equipment such as portable telephones.
The appended FIGS. 1 and 2 illustrate an integral-value adjustable frequency synthesizer and a fractional-value adjustable frequency synthesizer. A fractional-value adjustable frequency synthesizer is understood to be a frequency synthesizer whose frequency can be adjusted by integral or non-integral multiples of a reference frequency. Such devices are known per se and illustrated, for example, by the documents (1), (2) and (3), whose complete references are stated at the end of the description.
FIG. 1 indicates the basic structure of a frequency synthesizer, which is constructed around a phase-locked loop 10. The phase-locked loop comprises, in essence, a voltage-controlled oscillator 12, a frequency divider 14, a phase-frequency comparator 16 and a loop filter 18.
The voltage-controlled oscillator 12, referred to as  less than  less than VCO oscillator greater than  greater than  in the following of the text, delivers an output signal whose frequency cannot be increased or reduced as a function of a control voltage applied to its input. This control voltage is produced by the phase-frequency comparator 16, which is connected to the input of the VCO oscillator 12 via the loop filter 18.
The phase-frequency comparator 16 compares the frequency (or phase) of a signal delivered by the frequency divider 14 and the frequency of a reference signal delivered in the example of the Figure by a quartz device 20. When the frequency of the signal delivered by the frequency divider is lower than that of the reference signal, the phase-frequency comparator associated to the loop filter 18 produces a voltage instructing the frequency of the VCO oscillator 12 to be increased. Conversely, the frequency of the VCO oscillator is reduced when the frequency of the signal delivered by the frequency divider is higher than that of the reference signal.
The frequency divider 14 is a device constructed around a certain number of flip-flops and can thus divide the frequency of the signal of the VCO oscillator 12 only by integral values. The dividing ratio, which is adjustable by integral values, is an integer referred to as N. An adjusting input, indicated by an arrow 22, enables to fix the value N.
The frequency of the VCO oscillator, referred to as FVCO is thus such that:
FVCO=N*Fref,xe2x80x83xe2x80x83(1) 
where FREF is the frequency of the reference signal delivered by the quartz device 20.
It is observed that a modification by unity of the value of the dividing ratio N (integral) provokes a variation equal to Fref of the frequency of the VCO oscillator. Accordingly, it is impossible to adjust the frequency of the VCO oscillator 12 with a resolution higher than Fref. In the case where the frequency of the reference signal is high, this resolution may turn out to be insufficient.
A much finer adjustment of the frequency of the output signal of the loop 10, that is to say, of the frequency of the signal delivered by the VCO oscillator 12, may be obtained with a frequency synthesizer in accordance with FIG. 2.
The frequency synthesizer shown in FIG. 2 comprises a phase-locked loop 10 which includes the same elements as those of loop 10 of FIG. 1.
The frequency divider 14, on the other hand, has not only an adjusting input 22 for fixing the value N of the dividing ratio, but also a switch input 24 for switching the dividing ratio between two or more consecutive values around the value N. In the example of FIG. 2, the switch input 24 of the frequency divider 14 enables to switch the dividing ratio between two values, which are N and N+1.
The switch input 24 is connected to a sigma-delta modulator 30 and, to be more precise, to an overflow-carry terminal 32 of this modulator.
The sigma-delta modulator 30 which, in the example of the Figure, is a first-order digital modulator with a word adder 31, has a first digital input 34 for an adjusting instruction referred to as K. The adjusting instruction is added to a digital value delivered by a shift register 36 of the modulator. The register 36 is clocked by the output signal of the frequency divider 14, and receives the output of the word adder 31. It is connected to a second digital input 38 of the adder. When the sum of the adjusting instruction and of the output of the register 36 is lower than a digital capacity of the adder 31, the overflow-carry adopts the logic 0 value, for example. On the other hand, when the sum is higher than the capacity of the adder 31, the overflow-carry adopts the complementary logic 1 value in that case.
The frequency divider 14 is arranged for performing a frequency division with a first dividing ratio when its switch input 24 receives the first logic state and for performing a division with a second dividing ratio which is different from +/xe2x88x921, when the input 24 receives the second switching state.
In the example described, the dividing ratio is N for a logic 0 state and N+1 for a logic 1 state.
Although at any instant the dividing ratio of the frequency divider is an integer, the repeated switching of the ratio between N and N+1 enables to obtain a resulting mean dividing ratio comprised between these two values, that is to say, a non-integral ratio.
In a more precise way, one has:             F      VCO        =                  1                              T            N                    +                      T                          N              +              1                                          ⁡              [                                            T              N                        *            N            *                          F              ref                                +                                    T                              N                +                1                                      *                          (                              N                +                1                            )                        *                          F              ref                                      ]                        that      ⁢              xe2x80x83            ⁢      is        ,          
        ⁢                  F        VCO            =                        [                      N            +                                          T                                  N                  +                  1                                                                              T                  N                                +                                  T                                      N                    +                    1                                                                                ]                *                  F          ref                    
In these expressions, TN and TN+1 are the periods during which the dividing ratio is equal to N and N+1, respectively.
Considering that the adjusting instruction K applied to the first input 34 of the sigma-delta modulator is coded in L bits, and that the maximum capacity of the adder is 2Lxe2x88x921, a fractional part of the dividing ratio equal to K/2L can be defined. The fractional component K/2L is further denoted k in the following of the text. One has:                               F          VCO                =                              [                          N              +                              K                                  2                  L                                                      ]                    *                      F            ref                                              (        2        )            
For low values of the adjusting instruction (K≅0) the output frequency is close to Fref*(N) and for high values of the adjusting instruction (K≅2L) the output frequency is close to Fref*(N+1).
Accordingly, it is possible to continuously adjust the frequency of the phase-locked loop between two values fixed by the choice of the dividing ratio N applied to the adjusting input 22 of the frequency divider 14 and by the choice of the adjusting instruction K applied to the sigma-delta modulator.
In the conventional phase-locked loops shown in FIG. 1, the oscillation frequency of the voltage-controlled oscillator may be adjusted via frequency xe2x80x9cstepsxe2x80x9d whose value is Fref. The xe2x80x9cstepxe2x80x9d thus corresponds to a variation of the dividing ratio from N to N+1 or from N to Nxe2x88x921. This clearly appears when reference is made to formula (1) indicated previously.
In order to obtain a relatively precise adjustment of the frequency of the loop, for example, the value of the frequency Fref of the reference signal is preferably chosen to be low. By way of a simple example, the frequency Fref, and thus the adjusting step, may be of the order of 200 kHz.
It may also be observed that a low reference frequency leads to retaining high values N of the dividing ratio. Indeed, it would be recollected that the frequency of the voltage-controlled oscillator is the product of the reference frequency (relatively low) and the dividing ratio N (relatively high).
The constraint of the choice of a relatively low value for the reference frequency does not exist, however, in a phase-locked loop as shown in FIG. 2.
The formula (2) given earlier actually shows that it is possible to adjust the frequency by making the value of the fractional part k vary, that is to say K/2L. The adjusting step may thus be that Fref/2L. For an 8 or 16-bit coding, that is to say, for L=8 or L=16, for example, the adjustment may be made nearly continuously and in a manner substantially independent of the reference frequency.
Thus, for phase-locked loops with a fractional divider, the reference frequency is preferably chosen to be very high. It is, for example, of the order of 26 MHz. A high frequency actually permits to correct the drifts of the loop in a finer way and thus permits a larger stability.
It may further be observed that the choice of a relatively high reference frequency permits to retain low values of N, that is to say, low values of the integral part of the dividing ratio.
The pulsation of its own of the phase-locked loop, denoted xcfx89n, may be expressed as a function of the gain KVCO of the voltage-controlled oscillator 12, of the gain Kxcfx86 of a charge pump of the phase-frequency comparator 16, of the capacitance C of a capacitor of the loop filter 18 and of the integral part N of the dividing ratio of the divider 22. The relationship is the following:                               ω          n                =                                                            K                VCO                            ·                              K                φ                                                    N              ·              C                                                          (        3        )            
Also the switch time ts of the phase-locked loop depends on the value xcfx89n of the pulsation of the loop. The switch time ts may be understood to be the time necessary for the loop to be set at a given pulsation oscillation system or the time necessary for switching from one pulsation or frequency value to another.
The switch time ts is linked with the pulsation via the following relationship:
ts=(2.5xc3x972xc3x97xcfx80)/xcfx89n 
By referring also to formula (3) of the pulsation xcfx89n indicated above, it is found that with an equal pulsation, relatively low values of the dividing ratio N, or at least all of its integral part, are to be compensated for by relatively high values of the capacitance C of the loop filter. Indeed, the values KVCO and Kxcfx86 are constant factors linked with the oscillator and with the charge pump of the phase-frequency comparator.
The choice of a high-value capacitor for the loop filter makes the influence of another time parameter t evident, which is the charge time of this capacitor. The loop filter may be considered a passband filter with a capacitor capable of converting a current i, not frequency filtered, of the charge pump of the phase frequency converter and a voltage Vtune, frequency filtered, and used for controlling the VCO oscillator. The charge time t of the capacitor C is linked with the current i and with the voltage Vtune via the following relationship:
t=Cxc3x97Vtune/ixe2x80x83xe2x80x83(4) 
In this expression, C is the capacitance of the loop filter.
The charge time t of the capacitor will be added to the switch time ts previously mentioned and is likely to be unfavorable for the tuning speed of the loop at a desired frequency. This problem is specific of the loops which comprise a fractional divider, that is to say, loops controlled via a high reference frequency and having a low dividing ratio N.
The state of the art is further illustrated via documents whose references are stated at the end of the description.
It is an object of the invention to propose a frequency synthesizer and a corresponding method of frequency synthesis, which do not have the limitations recalled above.
It is more particularly an object of the invention to propose a frequency synthesizer of the type having a fractional divider, capable of operation with a high reference frequency and having a very brief overall switch time.
It is another object of the invention to propose such a synthesizer in which it is not necessary to resort to a multiplication of the number of charge pumps or to the overdimensioning of the charge pump providing the phase frequency converter with a phase-locked loop.
It is a further object of the invention to propose such a synthesizer which is to a large extent freed from the dispersion of characteristic features of the components and of the influence of thermal drifts.
To achieve these objects, the invention more precisely has for its object a frequency synthesizer comprising in a phase-locked loop:
a phase-frequency comparator connected to a reference frequency source,
at least a voltage-controlled oscillator, and
a fractional frequency divider suitable for producing a mean dividing ratio with an integral part and a fractional part, the frequency divider being connected between the voltage-controlled oscillator and the phase-frequency comparator.
According to the invention the voltage-controlled oscillator comprises a plurality of oscillator stages which have different center frequencies, and the synthesizer comprises selection means for selecting an oscillator stage as a function of the integral part of the mean dividing ratio.
The invention is particularly applied to frequency synthesizers in which a frequency of a signal produced by the reference frequency source is higher and even very much higher than the frequency adjusting steps permitted by the frequency divider. This is the case for frequency synthesizers having a fractional divider.
By multiplying the number of VCO stages and selecting one of the stages, it is possible to assign to each stage a different center frequency and thus a different oscillation frequency band. These oscillation frequency bands, also called passbands, may thus be less wide than those of the complete oscillator or those of the oscillator of the prior art devices. While keeping the control voltage Vtune unchanged, and by using this voltage for the control of oscillator stages that have narrower passbands, the gain KVCO of the various stages can be reduced. Indeed, the gain of an VCO oscillator or of a stage of an VCO oscillator is understood to be the ratio between the variation of the frequency and that of the control voltage (Vtune).
While reference is made to equation (3) of the pulsation of the phase-locked loop given in the introductory part of the text, it is found that a reduction of the gain KVCO permits with an equal pulsing value, a reduction of the value of the capacitance C of the loop filter. A capacitance C that is lower permits to reduce the charge time t. For this subject one may be referred to equation (4) also given in the introductory part.
While reference is still made to this same formula, it is observed that an increase of the current i would also have led to a reduction of the charge time t. On the other hand, this other solution, not retained by the invention, would have required a new concept of the charge pump of the phase frequency comparator to augment the intensity of the current i which it delivers.
It may further be observed that the various stages of the voltage-controlled oscillator have very brief switch times, not only because of their limited gain, but also because the frequency of the signal which they may deliver is generally closer to their center frequency which would not be the case with a single-stage oscillator.
Although this is not an absolutely necessary condition for the functioning of the synthesizer, it is, however, desirable that the passbands of the voltage-controlled oscillator stages are consecutive and pair-wise overlap.
The voltage-controlled oscillator may comprise a single VCO oscillator associated to a bank of capacitors or varactors used for the selection of the center frequency. A varactor is understood to be a component whose capacitance may be adjusted by a control voltage. Each capacitor or varactor thus forms with the VCO oscillator one of the oscillator stages. According to a variant, the voltage-controlled oscillator may also comprise a plurality of autonomous oscillators VCO which have, respectively, different center frequencies and form the various respective stages. The frequencies may in this case also be fixed by capacitors associated to the various VCOs.
In a particular embodiment of the synthesizer according to the invention, the selection means of the oscillator stages may comprise a logic table linking the respective integral parts of the dividing ratio selected for the frequency divider with choices of stages of the voltage-controlled oscillator.
The selection means may also comprise a logic pointer controlled by a data that corresponds to the integral part of the dividing ratio, to select a stage of the voltage-controlled oscillator on the basis of the logic table.
The logic table may comprise logic values, for example, in the form of binary codes, associated to values of N, and which may be used for controlling the opening or closing of switches. The switches are thus provided either for switching one of the stages formed of an autonomous VCO in the phase-locked loop, or for selecting one or various capacitors of a capacitor bank for modifying the center frequency of a VCO. The binary codes may also be used for a varactor voltage control.
According to a perfected embodiment of the synthesizer according to the invention, this synthesizer may comprise calibration means associated to the selection means of the stages of the voltage-controlled oscillator. Thanks to the calibration, the synthesizer may be freed from the scatterings of the characteristics of the VCO oscillator, which may result from the manufacture of its components or from their sensitivity to temperature. The calibration may take place when the device is turned on or possibly with each change of frequency. The calibration means may comprise, for example, a first and a second counter clocked by the voltage-controlled oscillator and by the reference frequency source, respectively, a subtracter connected to the counters for establishing a counting difference, and means for correcting the selection as a function of the counting difference.
The use of two counters is a particularly economic and reliable solution for controlling the frequency of the stages of the VCO. It further permits to establish directly a correction instruction which the counting difference is.
To take the correction instruction into account, the calibration means may comprise an adder for adding the counting difference to the integral value of the mean dividing ratio N and for applying this sum to the logic selection table of the stages of the voltage-controlled oscillator. The calibration means may also comprise a shift register of the digital selection values of the stages of the voltage-controlled oscillator, written in the logic selection table.
The invention also relates to a method of synthesizing frequencies by means of a frequency synthesizer, comprising in a phase-locked loop:
a phase-frequency comparator connected to a reference frequency source,
at least a voltage-controlled oscillator, and
a fractional frequency divider suitable for producing a mean dividing ratio with an integral part and a fractional part, the frequency divider being connected between the voltage-controlled oscillator and the phase-frequency comparator,
in which the voltage-controlled oscillator comprises a plurality of oscillator stages which have different center frequencies. According to the method, one of the stages of the voltage-controlled oscillator is selected as a function of the integral value of the mean dividing ratio.
Finally, the invention relates to a frequency converter equipped with the frequency synthesizer according to the invention, and its use in a portable telephone.
Other characteristic features and advantages of the invention pertain to the description that will follow, and have reference to the appended drawing Figures. This description is given in a purely illustrative and non-limitative capacity.